1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in a form of a lateral DMOSFET.
2. Description of the Background Art
There are two types of a conventional power DMOSFET device, including a vertical DMOSFET (VDMOS) which has a drain electrode on a back side of a substrate, and a lateral DMOSFET (LDMOS) which has a drain electrode formed on a top side of a substrate by using an n-type buried layer and an n.sup.+ -type diffusion layer.
Now, an example of a conventional n-channel type VDMOS shown in FIG. 1 will be described.
In this n-channel type VDMOS, an n.sup.+ -type diffusion layer 4 functioning as a source region is formed inside a p-type diffusion layer 3, which is formed inside an n-type epitaxial layer 2 formed on an n.sup.+ -type silicon substrate 12. Also, on a top side of the n-type epitaxial layer 2, a gate electrode 7 is formed on a gate insulation film 6 formed over the p-type diffusion layer 3 functioning as a channel region and the n.sup.+ -type diffusion layer 4 functioning as a source region. The gate electrode 7 is covered by an interlayer insulation film 8, over which a source electrode 16 is formed. In addition, on a back side of the n.sup.+ -type silicon substrate 12 which functions as a drain region, there is formed a drain electrode 13.
In such a VDMOS, the source electrode 16 and the drain electrode 13, which are main passages for the current, are separately provided on the top and back sides of the substrate 12, so that there is no need to collect the current planewise. As a result, the resistance and the area loss due to these components are reduced such that there has been an advantage that the on resistance can be lowered considerably.
However, such a VDMOS has been associated with the following problems.
First, because the drain region is formed by the n.sup.+ -type silicon substrate 12, it has been difficult to form a plurality of VDMOSs on a single substrate, and operating each of them independently, or to form a VDMOS along with other devices such as a CMOS or a bipolar IC.
Secondly, the on resistance is parasitically introduced into the substrate resistance in such a VDMOS.
It has recently become popular in the VDMOS to reduce the on resistance by using finer p-type diffusion layer 3 and n.sup.+ -type diffusion layer 4 manufactured by the improved fine manufacturing technique.
On the other hand, an example of one type of a conventional n-channel type LDMOS is shown in FIG. 2, which will now be described.
In this n-channel type LDMOS, an n.sup.+ -type diffusion layer 4 is formed inside a p-type diffusion layer 3, which is formed inside an n-type epitaxial layer 2 formed on a p-type silicon substrate 1. Also, on a top side of the n-type epitaxial layer 2, a gate electrode 7 is formed on a gate insulation film 6 formed over the p-type diffusion layer 3 functioning as a channel region and the n.sup.+ -type diffusion layer 4 functioning as a source region. The gate electrode 7 is covered by an interlayer insulation film 8, over which a source electrode 16 is formed. In addition, there is provided an n-type diffusion layer 15 which is making a contact with an n.sup.+ -type buried layer 14 formed between the p-type silicon substrate 1 and the n-type epitaxial layer 2, and an n.sup.+ -type diffusion layer 5 is formed inside the n-type diffusion layer 15, such that a drain electrode 17 can be formed over the n.sup.+ -type diffusion layer 5 on a top side of the p-type silicon substrate 1.
In such an LDMOS, because it is entirely formed on the grounded p-type silicon layer 1, there has been advantages that such an LDMOS can be formed along with the other electrically isolated devices or LDMOSs, and the effect of the substrate resistance on the on resistance is very small.
However, there has also been a problem that the device area have to be enlarged in order to incorporate the n-type diffusion layer 15 and the drain electrode 17. The area required for this reason needs to be as large as that covered by the source electrode, in order to have the drain current flow.
Now, the reduction of the on resistance by using the improved fine manufacturing technique, popularly exercised for a VDMOS as already mentioned above, is not effective in reducing the dead space in the LDMOS, so that the extent by which the on resistance can be reduced has been rather limited in the LDMOS.
Also, in this type of LDMOS, there has been a problem that although the substrate resistance is very small, the parasitic drain resistance due to the resistance of n-type diffused layer and n.sup.+ -type buried layer is large. This parasitic drain resistance can be reduced effectively by enlarging the total area of the n-type diffusion layer 15 so as to reduce the distance that the current have to travel through the n.sup.+ -type buried layer 14. However, this in turn increases the dead space in the LDMOS.
Thus, the on resistance in this type of the LDMOS has usually been over twice as large as the VDMOS of the same device area. For this reason, the use of this type of the LDMOS has been limited to cases involving a small or medium amount of current only. For a case involving a large amount of current such as that over 10A, the device area of the LDMOS becomes practically too large.
There is also another type of an LDMOS in which the current flows along the substrate surface, which is shown in FIG. 3 and will now be described.
In this LDMOS of FIG. 3, a p-type diffusion layer 3 functioning as a channel region and an n.sup.+ -type diffusion layer 5 functioning as a drain contact region are formed inside an n-type epitaxial layer 2 formed on a p-type silicon substrate 1. Inside the p-type diffusion layer 3, n.sup.+ -type diffusion layer 4 functioning as a source region is formed. Also, on a top side of the p-type silicon substrate 1, a gate electrode 7 is formed on a gate insulation film 6 formed over the p-type diffusion layer 3 and the n.sup.+ -type diffusion layer 4. The gate electrode 7 is covered by an interlayer insulation film 8, over which a source electrode 16 is formed. In addition, over the n.sup.+ -type diffusion layer 5, a drain electrode 17 is formed on a top side of the p-type silicon substrate 1.
In such an LDMOS, just as in the LDMOS of FIG. 2 described above, because it is entirely formed on the grounded p-type silicon layer 1, there is an advantage that such an LDMOS can be formed along with the other electrically isolated devices or LDMOSs.
Furthermore, in this type of the LDMOS, the parasitic drain resistance can be reduced as there is no n.sup.+ -type buried layer 14 through which the current have to pass.
However, this type of the LDMOS is also associated with the problem of the enlargement of the device size due to the inclusion of the n.sup.+ -type diffusion layer 5 and the drain electrode 17, which gives rise to the problem of the larger dead space for the larger current capacity, as in the LDMOS of FIG. 2.
Moreover, in this type of the LDMOS, it is necessary to form the source region 4 and a base region contact window 3' on a surface of the p-type diffusion layer (base region) 3, so that the mask matching becomes necessary, and therefore the base region 3 can be made smaller only to a limited extent.
Thus, the on resistance in this type of the LDMOS has also usually been over twice as large as the VDMOS of the same device area.
There is also a proposition of a double layer structure for this type of the LDMOS as shown in FIG. 4, in which a source electrode 11 and a drain electrode 9 are formed in a shape of a double layer with an intermediate insulation layer 10 formed between the source electrode 11 and the drain electrode 9.
Such an LDMOS having a double layer structure has an advantage of being capable of reducing the area due to the drain electrode. However, this type of the LDMOS also has a necessity to form the source region 4 and a base region contact window 3' on a surface of the p-type diffusion layer (base region) 3, just as in the LDMOS of FIG. 3, so that the mask matching becomes necessary, and therefore the base region 3 can be made smaller only to a limited extent.
Thus, the conventional LDMOS is known to be advantageous in that it is suitable for being integrated with the other devices or made into multiple output configuration, as it has the drain electrode on the top side of the substrate, but it also has the problem of having the higher on resistance compared with the VDMOS which has the drain electrode on the back side of the substrate, such that it is less desirable in terms of costs, as well as in terms of the limit on the current capacity.
Also, in the LDMOS, since the current flows mostly on the top side of substrate, the effect of the substrate resistance becomes small. However, the device area have to be enlarged in order to incorporate the drain electrode 17.